1. Field of the Invention
The present invention relates to a subtracting circuit providing a difference between an analog input voltage and a voltage dropped by a load, and to an A/D converter including the subtracting circuit.
2. Description of the Background Art
An analog voltage subtracting circuit provides a difference between an analog input voltage and a voltage dropped by a load, and it is used in an A/D converter, for example. FIG. 10 is a block diagram of a conventional subtracting circuit. The subtracting circuit A shown in FIG. 10 includes an analog voltage receiving terminal 1, an output terminal 2 outputting the result of subtraction, a load 3' and an D/A converter 6. An analog voltage generator 7' is connected to the analog voltage receiving terminal 1. The analog voltage generator 7' applies a DC voltage V1 to the analog voltage receiving terminal 1. The load 3' has one end 5 connected to the analog voltage receiving terminal 1 and the other end 4 connected to the output terminal 2. Passive element such as a resistor, a capacitor or an inductance, or active element such as a diode or a transistor may be used as the load 3'. If a passive element is used, linear output voltage is provided, and if an active element is used, non-linear output voltage is provided. The D/A converter 6 has a positive output terminal 6a connected to the other end 4 of the load 3' and a complementary output terminal 6b coupled to the supply potential Vcc. The D/A converter 6 generates a positive output current Iout in response to a bit signal designating the magnitude of the externally applied positive output current, and applies this to the other end 4 of the load 3' through the positive output terminal 6a.
The operation of the subtracting circuit shown in FIG. 10 will be described. The output voltage V2 can be ideally represented by applying Ohm's law, EQU V2=V1-Iout.multidot.Z (1)
Where V1 represents the voltage at the analog voltage receiving terminal 1, V2 represents the voltage at the output terminal 2 and Z represents impedance of the load 3'. Namely, the dropped voltage Iout.multidot.Z is subtracted from the input voltage V1.
However, the equation (1) can be applied only to an ideal case. Actually, the resistance of the output stage of the analog voltage generator 7' is limited, and because of this influence, the voltage V2 at the output terminal 2 becomes non-linear, which will be described in detail later.
An A/D converter capable of high speed operation and having high resolution is in strong demand especially in the field of image processing. An A/D converter having conversion frequency higher than 50 MHz and the resolution of 10 bits is necessary for transmitting high definition television signals. If such an A/D converter is formed by a flash A/D converter, the input capacitance, chip area and power consumption are increased. In order to solve this problem, recently a serial-parallel type A/D converters have been developed, in which an analog input voltage is divided into higher and lower bits to be subjected to A/D conversion. The above described subtracting circuit is used in this serial-parallel type A/D converter.
FIG. 11 is a block diagram of the serial-parallel type A/D converter, and FIG. 12 is a schematic diagram showing the output stage of the sample hold circuit 7 and the subtracting circuit A of FIG. 11.
Referring to FIG. 11, the A/D converter includes a sample hold circuit 7, an A/D converter 10 for the higher bits, a subtracting circuit A, an amplifier 11 and an A/D converter 12 for the lower bits. The sample hold circuit 7 samples and holds the analog input voltage Vin and outputs an analog voltage V1. The A/D converter 10 for the higher bits roughly A/D converts the analog voltage V1 output from the sample hold circuit 7 to provide higher bits.
The subtracting circuit A includes a resistor 3 as a load, and a D/A converter 6. The resistor 3 has one end 5 connected to an output of the sample hold circuit 7 and the other end connected to the A/D converter 12 for the lower bits. The D/A converter 6 generates a positive output current Iout for generating a desired drop of voltage in the resistor 3 in response to the higher bits calculated by the A/D converter 10 for the higher bits, and applies the same to the other end 4 of the resistor 3. In other words, the subtracting circuit A calculates the difference between the analog voltage V1 output from the sample hold circuit 7 and the voltage value corresponding to the higher bits calculated by the A/D converter 10 for the higher bits.
Referring to FIG. 12, the output stage of the sample hold circuit 7 includes a transistor 7d and a current source 7e. The transistor 7d has its collector connected to a supply terminal Vcc, its base connected to receive the sampled and held signal, and its emitter connected to the current source 7e and to the analog voltage receiving terminal 1.
The current source 7e applies a DC current I7 to the emitter of the transistor 7d. The D/A converter 6 includes switching circuits S1-S8, which switch in response to the higher bit signals from the A/D converter 10 for the higher bits (FIG. 11), and current source 61-68 connected to the corresponding switching circuits. Each of the switching circuits S1-S8 includes two input terminals and one output terminal. One input terminal is connected to the positive output terminal 6a, and the other input terminal is connected to the complementary output terminal 6b. The output terminals of the switching circuits S1-S8 are connected to the corresponding current sources 61-68. The current sources 61-68 generate the current of the same magnitude.
Therefore, the sum of the positive output current Iout and the complementary output current Iout is constant, and the positive output current Iout and the complementary output current Iout are complementary to each other. The sum will be referred to as a full scale current Ifs in the following.
FIG. 13 shows the ideal input/output characteristic and the actual input/output characteristic of the A/D converter shown in FIGS. 11 and 12. The dotted line represents the ideal input/output characteristic, while the solid line represents the actual input/output characteristic.
The operation of the A/D converter will be described with reference to FIGS. 11 to 13.
The analog input voltage Vin is sampled and held by the sample hold circuit 7, and an analog voltage V1 is generated. The analog voltage V1 is applied to the higher A/D converter 10 and to the resistor 3. The output voltage V1 applied to the higher A/D converter 10 is subjected to rough A/D conversion. The A/D converted value (higher bit signal) is applied to each of the switching circuits S1-S8 of the D/A converter 6. The switching circuits S1-S8 switch in response to the higher bit signals. FIG. 12 shows an example in which the higher bit signal is "101" and five switching circuits S1-S5 are on. In response to the switching operation of the switching circuits S1-S8, a positive output current Iout corresponding to the bit signal is generated, and the positive output current Iout thus generated flows to the resistor 3. Consequently, a voltage V2 which is ideally represented by EQU V2=V1-Iout.multidot.R (2)
is output, where R represents the resistance value of the resistor 3.
In this manner, the dropped voltage caused by the resistor 3 can be subtracted from the analog voltage V1. The input/output characteristic represented by the equation (2) is shown by the dotted line in FIG. 13.
However, the transistor 7d of the output stage constitutes an emitter follower circuit, and there is a limited output resistance between the base and the emitter, which output resistance is non-linear. Not only the emitter follower circuit but circuitry using non-linear element such as a transistor has non-linear output.
The non-linear input/output characteristic of the above mentioned emitter follower circuit will be described in greater detail. The following approximation is widely known where Vb represents the base voltage of transistor 7d, Ic represents the collector current, Ie represents the emitter current and .alpha. represents the rate of amplification of base-ground current: EQU Ic=Is.multidot.exp {(Vb-V1)/Vt}=.alpha. (3)
Is represents saturation current, Vt represents a thermal voltage, and these values and .alpha. are multipliers not dependent on other variables. From the equation (3), V1 can be represented as EQU V1=Vb-Vt.multidot.Log (.alpha..multidot.Ie/Is) (4)
The emitter current Ie is the sum of the current I7 of the current source 7e and the positive output current from D/A converter 6, and therefore, EQU V1=Vb-Vt.multidot.log {.alpha..multidot.(I7+Iout)/Is} (5)
Thus the analog voltage V1 changes non-linearly dependent on the positive output current Iout, and as a result, the output voltage V2 represented by the equation (2) also becomes non-linear. This is shown by the solid line in FIG. 13. When the value of the analog voltage V1 with Iout=0 is represented by V10, this value is calculated as EQU VT10=Vb-Vt.multidot.log (.alpha..multidot.I7/Is) (6)
Since the conventional subtracting circuit and the A/D converter are structured as described above, the analog voltage V1 and the output voltage V2 change non-linearly dependent on the change in the output of the D/A converter. Consequently, precise result of subtraction can not be obtained, causing errors in the result of A/D conversion.